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stb03_sds_0323.fm.00 march 23, 2000 ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers features page 1 of 54 features overall ? high-end set-top box technology ? four major subsystems integrated with ibm a on-chip coreconnect ? structure. ? maximum mips for os and application tasks ? simpli?ed driver and software development ? scalable, ?exible, and extendible ? 108 mhz/150 mips and 162 mhz/225 mips versions available ? 3.3 v and 2.5 v power supplies ? ibm cmos sa-12e (0.25 m m) process technology ? 304-pin pbga package mpeg-2 digital audio/video subsystem ? mpeg-2 video decoder ? mpeg-2 audio decoder ? mpeg-2 transport/dvb descrambler ? dolby a digital audio 1 support on selected parts ? macrovision copy protection on selected parts ? display controller ? digital encoder (denc) with six outputs ? anti-flicker filter powerpc 405 ? host processor: ppc405b3 cpu ? 16kb instruction, 8kb data caches ? universal interrupt controller memory subsystem ? dma controller ? cross-bar switch ? external bus interface unit (ebiu) ? ide interface ? two sdram controllers peripheral subsystem ? general purpose timers (gpts) ? pulse width modulators ? 1284 parallel port ? two smart card controllers ?two i 2 c interfaces ? 16550 serial communications port ? infrared serial communications port ? general purpose input/output (gpio) ? serial controller port ? modem serial interface/digital audio input description ibm stb03xxx digital set-top box integrated con- troller family are highly integrated silicon devices specifically developed for digital set-top box (stb) applications using industry-leading ibm cmos sa- 12e (0.25 m m) process technology. the stb03xxx is part of the second generation of ibm products for digital stb applications. powerpc processing and peripheral i/o architecture provide a high level of performance and functionality when used in audio and video subsystems. the resulting stb technology is full-functioned and easy to use. the stb03xxx minimizes host processor interven- tion to maximize mips for operating system and application tasks. most of the features required in the back end of typical midrange and high-end stbs are integrated. driver and software develop- ment is facilitated while preserving scaleability, flex- ibility, and extendibility. architecturally, the devices consist of four sub- systems interconnected and tuned using corecon- nect, the ibm multiple-bus, on-chip interconnect structure: 1. powerpc host processor 2. digital audio/video 3. memory interface 4. peripheral these high performance subsystems are suited to advanced interactive stbs with demanding soft- ware requirements including web browsers and java ? . 1. this implementation has not yet completed the evaluation process by dolby laboratories and is offered subject to obtaining approval. a dolby digital audio license is required from dolby laboratories. ( datasheet : )
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary ordering information page 2 of 54 stb03_sds_0323.fm.00 march 23, 2000 conventions and notation throughout this document, standard ibm notation is used, meaning that bits and bytes are numbered in ascending order from left to right. thus, for a 4-byte word, bit 0 is the most significant bit and bit 31 is the least significant bit. overbars, e.g. txenb, designate signals that are active low. numeric notation is as follows: hexadecimal values are in single quotes and preceded by "x" or "x." for example: x0b00. binary values are spelled out (zero and one) or appear in single quotes and preceded by a "b." for example: b10101. settings of a bit or field are binary numbers but are often displayed in tabular form without quotes or the pre- ceding "b." for example: 00 : 30 frames per second 01 : 15 frames per second 11 : 10 frames per second ordering information part number performance (est.) clock speed audio copy protection ibm39stb03200pbb09c 150 mips 108 mhz mpeg none ibm39stb03201pbb09c macrovision 2 ibm39stb03210pbb09c mpeg/dolby digital 1 none ibm39stb03211pbb09c macrovision 2 ibm39stb03400pbb06c 225 mips 162 mhz mpeg none ibm39stb03401pbb06c macrovision 2 ibm39stb03410pbb06c mpeg/dolby digital 1 none ibm39stb03411pbb06c macrovision 2 1. these parts include dolby digital enabling software and require the user to obtain a license from dolby laboratories licensin g corporation. please see dolby digital licensing on page 3. 2. these parts support macrovision copy protection and require that a license be in effect between the purchaser and macrovision corporation. please see macrovision licensing on page 3.
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 licensing requirements page 3 of 54 licensing requirements dolby digital licensing dolby digital audio enabling software is provided with the ibm39stb0321x and ibm39stb0341x products. dolby is a trademark of the dolby laboratories. supply of this implementation of dolby technology does not convey a license or imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use this implementation in any end-user or ready-to-use final product. companies planning to use this implementation in products must obtain a license from dolby laboratories licensing cor- poration before designing such products. additional per-chip royalties may be required and are to be paid by the purchaser to dolby laboratories, inc. details of the oem dolby digital license may be obtained by writing to: dolby laboratories inc. dolby laboratories licensing corporation attn: intellectual property manager 100 potrero avenue san francisco, ca 94103-4813 macrovision licensing macrovision copy protection is supported in the ibm39stb032x1 and ibm39stb034x1 products. these devices are protected by u.s. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual property rights. the use of macrovisions copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. a valid macrovision license must be in effect between the stb03xx1 purchaser and macrovision corporation. additional per-chip royalties may be required and are to be paid by the purchaser to macrovision corporation. macrovision corporation 1341 orleans avenue sunnyvale, ca 94089
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary architecture and subsystem information page 4 of 54 stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information block diagram opb bridge ppc405b3 16k-i cache 8k-d cache dma controller video decoder 2d/3d graphics nim descrambler audio d/a plb0 plb1 crossbar dvb descrambler audio decoder trace flash transport jtag smart opb bus serial1/ gpt card0 serial modem i 2 c1 i 2 c0 gpio sdram0 sdram smart card1 ext digital interrupts per. device sram serial0/ 16550 infrared control port interface ebiu controller sdram sdram1 controller pwm ide uic rom osd dac ieee 1284 encoder digital encoder cpu iec-60958
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information page 5 of 54 powerpc 405b3 host processor subsystem the powerpc 405b3 (ppc405b3) subsystem handles all system initialization and control and also provides power and flexibility for product differentiation. powerpc 405b3 cpu the ppc405b3 provides high performance and low power consumption. the cpu executes at sustained speeds of greater than one cycle per instruction at 108 or 162 mhz. interrupt latency is three cycles, the best time for critical interrupts. ppc405b3 subsystem risc execution unit cache timers: pit, fit, 64-bit base core clocking multiplier/divider thirty-two 32-bit gprs cpu ppc405b3 processor plb master controls cache controls 8kb i-cache array interrupt controller interface interfaces uic interrupts plb master clocks power mgmt dcrs jtag (see note) note: the jtag interface is used for development. 16kb d-cache array data instruction mmu
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary architecture and subsystem information page 6 of 54 stb03_sds_0323.fm.00 march 23, 2000 on-chip instruction is compatible with powerpc user instruction set architecture, with branch prediction exe- cution for most instructions. there are 32 x 32 bit general purpose registers. instruction and data cache arrays improve system throughput. the cpu has a separate two-way set-associative 16kb instruction cache and an 8kb write-back/write-through data cache. multiply and divide instructions are performed in hardware and are not emulated in software. universal interrupt controller the universal interrupt controller (uic) provides all necessary control, status, and communication functions between all sources of interrupts and the ppc405b3. the uic combines stb03xxx interrupts and presents them to the ppc405b3s critical or non-critical inputs. all interrupts can be programmed to generate either critical or non-critical output. interrupts can be level- or edge-sensitive and interrupt polarity is programmable. an optional read-only vector is used to reduce critical interrupt servicing latency. this vector is generated by combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and a vector base address register. a configurable priority control bit determines whether the least significant or most significant bit in the status register has the highest priority. clock and power management for power-saving purposes, a clock and power management (cpm) input is used to shut down clocks and device functions. a reset is required to activate a unit. memory interface subsystem the memory interface subsystem provides the system memory controller interface for sram, flash mem- ory, rom, and sdram. it also provides the direct memory access (dma) interfaces for these memories. a key advantage of the memory interface is its ability to gain concurrent access (one function to sdram0 and one function to sdram1) and mutual access (a given function can access either port). direct memory access controller the four-channel dma controller is a processor local bus master that allows faster data transfer between memory and peripherals than with program control. the controller supports memory-to-memory, peripheral- to-memory, and memory-to-peripheral transfers. the dma controller allows the ppc405b3 processor to exe- cute instructions with no bus contention when the ppc405b3 is executing from cache. dma is useful when memory subsystem plb1 plb0 dma ebiu sdram1 sdram sdram crossbar sdram0 ebiu flash, rom, etc.
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information page 7 of 54 the overhead associated with the controller setup is minimal compared to the time it would take to move data using program control load and store instructions. each dma channel has an independent set of registers for data transfer. the registers store data for control, source address, destination address, and transfer count. each channel also supports chained dma opera- tions, therefore every channel also includes a chained count register in which case source address registers function as chained address registers. all dma channels report their status to the dma execution unit. the dma controller also supports: ? internal dma channels for 1284 parallel port, smart card interface, 16550 serial communications control- ler, infrared communications controller, etc. ? 16- and 32-bit peripherals (on-chip peripheral bus and external) ? 32-bit addressing ? address increment or decrement ? internal data buffering capability ? memory-mapped peripherals processor local bus the processor local bus (plb) interfaces directly with the ppc405b3 and the other major subsystems (see block diagram, on page 4). the stb03xxx uses three plbs to provide high bandwidth between the function masters and the external memory interfaces for rom, flash, and sdram, etc. the stb03xxx plb architec- ture includes a crossbar switch to present both memory interfaces as flat, shared memory spaces . external bus interface unit the external bus interface unit (ebiu) expands the local bus to transfer data between the plb and a wide range of memory and peripheral devices attached to the external bus (see the following list). the ebiu can control up to eight devices or banks or regions of flash memory (128 mb), and a low latency maximizes system performance. the ebiu supports: ? a direct connect sram/rom/pia interface for - up to eight sram/rom/pia banks with programmable address select - programmable or device-paced wait states - burst mode (bme) and single-cycle transfers ? 16- and 32-bit byte addressable bus width ? programmable target word ?rst or sequential cache line ?lls ? ide interface ? supports ata-3 mode 4 register and pio transfers ? supports mode 2 multiword dma transfers (see ansi x3.298-1997, at attachment-3 interface (ata- 3)) ? dvb common interface support ? external bus master with support for device master and master/slave ? common bank-speci?c programmability ? device-paced ready input
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary architecture and subsystem information page 8 of 54 stb03_sds_0323.fm.00 march 23, 2000 sdram controller the sdram controller transfers data between the plb and up to two sdram memory banks attached to the external bus. the controller implements address and data pipelining and supports 16mb and 64mb sdrams concurrently. it also provides the following: ? direct-connect sdram interface ? high bandwidth with a narrow 16-bit interface ? page interleaving ? programmable address select ? programmable rates for automatic sdram refresh ? software-initiated and self refresh modes for power savings crossbar switch the plb crossbar switch (cbs) creates a flat memory model and implements unified memory architecture (uma), which connects multiple plb master buses to multiple plb slave buses, thus allowing two sets of plb buses to intercommunicate. processor, transport, and the audio and video decoders can access mem- ory through either memory controller. digital audio/video subsystem the mpeg-2 digital audio/video subsystem provides fully-synchronized playback of digital video and audio programs, with a minimum of interaction from the ppc405b3 processor. mpeg-2 video decoder with osd the mpeg-2 video decoder provides decompression, decoding, and synchronized playback of digital video streams with a minimum of host support. it produces interlaced video output and can support mpeg-2 com- pressed data streams up to an average rate of 15 mbps. the video decoder is also backward compatible to support the iso/iec international standard 11172-2 (11/93) (also called mpeg-1 standard). it supports the iso/iec 13818-2 main profile at main level. plb1 plb0 mpeg-2 mpeg-2 video decoder osd dolby digital audio decoder mpeg-2 transport dvb descrambler denc audio pll vcxo auxiliary auxiliary port nim to audio d/a and iec60958
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information page 9 of 54 the decoder also supports mpeg-2 mp@ml compliance with 2mb memory. only 2mb of memory are needed to decode full ccir601 resolution ntsc and pal encoded mpeg-2 bitstreams. it performs real-time decoding of all resolutions in 16-pixel multiples, up to and including 720x480x30 or 720x576x25. horizontal and vertical ?lters deliver high-quality video. chrominance ?ltering and up-sampling to provide ccir601 4:2:2 video output. pan and scan are supported in 1/16 pel accuracy for 16:9 source material. video rates range from 1.5 mbps to 15 mbps (higher in bursts). the mpeg-2 video decoder supports the european dvb standard and accepts packetized elementary or elementary mpeg-2 streams. it uses packetized elementary stream (pes) video decoding to extract the presentation time stamp (pts), and handles user data and other pes layer bit fields through memory access from the ppc405b3. input can be from transport or directly from system memory. outputs are pro- vided for video-only and for video-with-osd. the decoder can insert data in the vertical blanking interval (vbi) with vbi output support. it supports decod- ing of still or fixed images and display of scaled video images. it also features: ? letterbox format display ? selectable anti-?icker ?ltering ? output interface ?exibility (programmable controls) ? composite blanking and field id signals ? v-sync and h-sync signals ? ccir656 master and slave modes ? programmable signal polarity ? sophisticated error concealment ? 3:2 pull-down support. ? closed caption, teletext, or mixed (vps) ? (1/4x, 1/2x, 2x) and three graphic planes ? automated video channel change and time-base change features ? blending of external graphics. a multi-plane on-screen display (osd) uses bitmap data in memory to be merged with or displayed in place of the motion video data. three osd planes (the cursor, graphics and image planes) are provided for increased display flexibility. the osd includes: ? programmable background color ? multi-region link list graphic and image plane osd with a color table for each region ? programmable bitmap resolution on a region-by-region basis ? 64 x 64 pixel, 16-color cursor plane with blending controls ? overlay and video blending of graphic plane ? enhanced color mode for 24-bit color (yuv) in direct color and clut modes with 8-bit alpha blending ? video shading in graphic plane osd area ? osd control output for external multiplexer (picture-in-picture support) ? tiling capability in image and graphic planes ? scrolling of image and graphic planes ? horizontal scaling of image plane bitmaps ? animation support ? 16 mb osd addressing range to support more and larger bitmaps. mpeg-2 transport and dvb descrambler the mpeg-2 transport demultiplexer provides iso / iec 13818-1 mpeg-2 transport system layer demulti- plexing. its integrated digital video broadcasting (dvb) descrambler complies with dvb system layer require- ments and may be turned off for non-dvb applications. peak input rates are 100-mbps (parallel) or 60-mbps
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary architecture and subsystem information page 10 of 54 stb03_sds_0323.fm.00 march 23, 2000 (serial), or 88-mbps (parallel) or 60-mbps (serial) with the optional descrambler. packet identifier (pid) filter- ing is based on 32 programmable entries with detection and notification of errors and lost packets. hardware- based clock recovery on program clock references (pcrs) reduces processor load by: - calculating clock difference between pcr and system time clock (stc) - modulating output to drive an external vcxo - using an optional internal clock-recovery algorithm based on clock difference transport and descrambler features include: ? internal dvb (1.0 or 1.1) descrambler, including ?ltering and storage of eight control word pairs ? auxiliary output port for real-time data transfers: - 8-bit mode at 1x, 1/2x, 1/3x, 1/4x and 1/8x of the system clock speed ? table section ?ltering: - 64 separate 4-byte ?lter blocks with bit-level masking with full match/not match capability - multiple ?lters can be linked to extend ?ltering depth in 4-byte increments - multiple ?lters per pid - filters program-speci?c information (psi), service information (si), private tables - handles multiple sections per packet and sections that span packets - optional crc checking of section data ? selective routing of some or all packet data to system memory: - based on 32 separate queues (one per pid) - routing entire packets, payloads, adaptation ?elds, table sections (after ?ltering) and private data ? direct transfer of audio / video (pes) data to decoders ? simpli?ed channel changes, time-base changes and error ?agging / concealment through direct commu- nication with decoders ? interface for a transport assist processor to provide additional processing: - extended ?ltering / parsing of tables, private data, adaptation ?elds, and pes headers - ability to selectively route alternative data ?elds to system memory mpeg-2/dolby digital audio decoder the audio decoder receives and decodes either es (elementary stream) or pes (packetized elementary stream) audio data. the audio compute engine is a generic dsp processor that decodes mpeg, dolby digi- tal 1 , or 16-, 18- or 20-bit unformatted pulse code modulation (pcm) audio data via individual software pro- grams. the host processor downloads each program load to the audio decoder following initialization. the audio decoder generates up to two channels of decoded pcm for mpeg and pcm audio playback output. it pro- vides 2-channel mpeg audio output and 6-channel dolby digital down-mixed to either two channels or six channels of dolby digital output. unpacketized pcm (upcm) plays back at sampling frequencies of 16 khz, 22.05 khz, 24 khz, 32 khz, 44.1 khz, and 48 khz, along with quantization sample width selections of 16-, 18- or 20-bit input and 16 or 20-bit output. the audio decoder: ? decodes dolby digital, described in the atsc speci?cation digital audio compression (a/52). ? decodes mpeg-1 and mpeg-2 audio (layers i and ii) and 2-channel output, including single channel, stereo, joint stereo, and dual channel modes. 1. this feature available only on stb03x1x, dolby digital license required
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information page 11 of 54 ? performs mpeg-1 and mpeg-2 pes audio parsing, and also accepts audio elementary streams. parses and stores ancillary data into external memory for later use by the host processor. ? supports 16-khz, 22.05-khz, 24-khz, 32-khz, 44.1-khz, and 48-khz audio sampling frequencies. ? supports audio/video synchronization through pts/stc comparison with each audio frame. ? supports karaoke mode for dolby digital and pcm playback. ? supports an encoded audio bit rate up to 640 kbps. this bit rate only pertains to encoded bitstream data. ? includes audio clip mode for pes, es, and pcm formats with byte address granularity and 2mb maxi- mum per clip buffer. ? allows pcm mixing with primary audio stream input including sample rate conversion. pcm audio data supplied via secondary clip mode feature. ? supports expandable rate buffer size selectable from 4k to 64k (in 4k increments). ? uses a re-locatable rate buffer region, with a programmable base register (128-byte location granularity). ? has a re-locatable pts value and ancillary data region, using a programmable base register with 128- byte location granularity. ? uses a locatable audio temporary data and decoded audio data bank region (programmable base reg- ister with 128-byte location granularity with additional offset register). ? includes 256x and 512x dac sampling clock frequency con?gurations. ? has a programmable stream id register with corresponding 8-bit enable ?eld. ? provides three pcm output formats in 16- or 20-bit precision: -i 2 s - left-justi?ed - right-justi?ed ? performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchroni- zation or detection of crc errors. ? performs mpeg error checking using frame size calculation for each frame. ? provides de-emphasis pins that interface to external de-emphasis circuitry. ? provides dolby surround mode (dsurmod) pins that interface to external surround mode circuitry. ? provides a programmable interface that supports the following: - play, stop, and mute - rate buffer purge to support channel and mode changes - provides a compressed buffer full indicator - synchronization enable/disable for pts-stc comparison ? includes spdif meeting iec61937 and iec60958 specs. ? supports enhanced iec61937 s/p dif channel status bit by including 16 spdif channel status bits, with host control over most of the bits. ? inserts host-controlled validity bit into spdif sub-frame via dcr register.
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary architecture and subsystem information page 12 of 54 stb03_sds_0323.fm.00 march 23, 2000 ? performs audio attenuation in 64 steps, with smooth transitions between steps. ? provides tone generation with up to 128 generated tones at 31 different durations with seven levels of attenuation via processor command. ? supports automated channel change. ? supports automated time base change. ntsc/pal digital encoder unit with macrovision copy protection 1 the multi-standard digital encoder converts digital audio/video data into analog national television system committee (ntsc) or phase alternate line (pal) data output formats (see macrovision licensing on page 3). it provides up to six concurrent analog video outputs, including s-video, composite video, ypbpr, and rgb. the encoder is compatible with scart connectors, with support for macrovision copy protection revi- sion 7. analog outputs are driven by 10-bit d/a converters, operating at 27 mhz. the outputs drive standard video levels into 75- w loads. it s upports closed caption, teletext insertion, and line 23 wss (wide-screen signaling) per itu-r bt.1119. there is a switchable pedestal with gain compensation. playback of synchro- nized video data can be locked to the incoming composite video stream. additional interfaces external graphics and video (egv) port external graphics and video (egv) ports provide flexibility for interfacing external graphics and video compo- nents. when the egv is used as an output, its signals may be routed to an external graphics device or denc. when used as an input, either the internal osd graphics can be replaced with data from an external graphics device, or external digital video data (from an analog signal converted to digital via dsmd, for exam- ple) could replace the internally decoded mpeg video. in the latter case, the external digital video can be merged/blended with the internal osd graphics. 1. this feature is available only on stb03xx1, macrovision license required.
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information page 13 of 54 peripheral subsystem general purpose timer the general purpose timer (gpt) is an on-chip peripheral bus (opb) function that provides a separate time base counter and additional system timers beyond those defined in the ppc405b3. three inter-character (ic) time-out timers are also implemented in this functional unit in the gpt. these tim- ers receive the count signal inputs from other units they are timing. each timer is a 10-bit down counter loaded with a programmable value (tout) upon the active edge of the count signal input. once loaded, the ic timer counts down tout number of tclk cycles until it reaches zero (that is, when the ic timer has expired). when a timer expires, it sets its corresponding bit in the ic interrupt status register. there is a separate time base inside the gpt, distinct from the time base within the ppc405b3. two event timers capture unique input events and there are two compare timers with unique outputs. separately config- urable and programmable synchronization controls edge detection and output levels. there are two reset inputs, one for the entire gpt unit, and one for the time base. pulse width modulation the pulse width modulation (pwm) function produces two square wave outputs with a variable duty cycle under program control. the duty cycle varies from 100 percent to zero percent in steps of 1/256. there is a control register with two bits for each pwm. this register controls the active status of the pwm, and deter- mines what its inactive output level should be. when the pwm control register is set to disable a pwm, the 8- bit period counter will be inactive to minimize power. the pulse width modulation portion of the gpt contains two identical blocks, each containing an 8-bit pro- grammable and reloadable down counter and control logic. a time-base generator that is a free-running counter (tclk based) generates the frequency of the pulse-width modulated output. opb gpt / pwm peripheral subsystem other subsystems ieee 1284 smartcard (2) iic (2) 16550 serial com infrared serial com gpio serial control port ibm stb03xxx modem interface plb0 opb bridge
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary architecture and subsystem information page 14 of 54 stb03_sds_0323.fm.00 march 23, 2000 ieee 1284 parallel port the ieee 1284 parallel port is implemented as either the host side or peripheral side of the parallel port data bus. the parallel port bidirectional interface supports ieee std. 1284 extended capability port (ecp) 1 , byte 2 , nibble 3 , and compatibility 4 modes of operation. the parallel port also monitors ieee std. 1284 negotiation mode events, which allows the host to determine the capabilities of an attached peripheral and to set the interface into one of the four operational modes. the parallel port supports byte-wide fifo but does not sup- port enhanced parallel port (epp) mode. two direct memory access (dma) channels for transmit and receive allow independent data transfers from other peripherals. the ieee 1284 parallel port is compatible with existing parallel port hosts, and an inter-character time-out facility provides support with the gpt/pwm. inter-integrated circuit (iic) units two unique iic units are used to provide two independent iic interfaces and provide a simple to use, highly programmable interface between the opb and the industry standard iic serial bus. they provide full man- agement of all iic bus protocols, compliant with phillips semiconductors i 2 c speci?cation, dated 1995, and support a ?xed v dd iic interface. these iics can be programmed to operate as master, as slave, or as both master and slave on the iic interface. in addition to sophisticated iic bus protocol management, the iics pro- vide full data buffering between the opb and the iic bus. the iic units offe r 5 v tolerant i/o for both 100- and 400-khz operation with 8-bit data transfers and 7-bit and 10-bit address decode/generation. there is one programmable interrupt request signal, two independent 4 x 1-byte data buffers, and 12 memory-mapped, fully programmable configuration registers. smart card interface units the smart card interface units handle communications between an integrated circuit card and the host cpu. these 5 v tolerant i/o devices have a software-based control structure and are designed for use with asynchronous transmissions. they feature hardware activation/deactivation and reset with software over- rides and byte-wide fifo support. they are compatible with iso/iec 7816-3 and support t0 and t1 proto- cols. the interface units support 2-channel dma with 8-bit memory-mapped registers and hardware error checking. an inter-character time-out facility provides timing support from the gpt/pwm. 16550 serial communication controller the 16550 serial communication controller is a universal asynchronous receiver/transmitter (uart) with fifos, and is compatible with the 16550 part numbers manufactured by national semiconductor (ns) corpo- ration. it is also compatible with national semiconductor 16450 (non-fifo version). serial interface charac- teristics are fully programmable with complete modem control functions and status reporting capability. the controller supports: ? 5-, 6-, 7-, or 8-bit characters ? even, odd, or no parity bit generation and detection ? 1-, 1.5-, or 2-stop-bit generation ? variable baud rate and a programmable baud rate generator 1. ecp refers to the extended capability port. an asynchronous, byte-wide, bidirectional channel. 2. byte refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host. 3. nibble refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host. 4. compatibility refers to an asynchronous, byte-wide forward (host-to-peripheral) channel.
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 architecture and subsystem information page 15 of 54 there is also support for two dma channels with a 16-byte fifo for transmit/receive path. internal loopback is provided for diagnostics and an inter-character timeout facility provides timing support from the gpt/pwm. infrared serial communications controller in addition to standard uart functions, the serial/infrared communications controller can use an alternate mode (irda mode) to transfer and receive infrared characters. irda transmissions are specified by the infra- red data association (irda) specification 1.1. irda mode supports rs-232 and infrared communications up to 1.152 mbps with automatic insertion/removal of standard async communication bits. the controller includes: ? a programmable baud rate generator ? individual enable for receiver and transmitter interrupts ? internal loopback and auto-echo modes ? full-duplex operation ? programmable serial interface ? status reporting capability ? individual receiver and transmitter dma support ? auto-handshaking mode for receiver and transmitter ? transmitter pattern generation capability ? serial clock frequency up to 1/2 system clock frequency ? inter-character timeout facility support from the gpt/pwm modem interface the modem interface provides a glueless communication from the device to and from many standard and economical telephony codecs (note: codecs are the audio adc/dac devices). the ppc405b3 cpu and applicable software can be used to implement an inexpensive interface for a modem. the external interface supports industry standard 4-wire parameters, consisting of transmit data, receive data, clock, and frame sync. two channels of dma allow off-loading data from the cpu. the modem interface supports digital audio mic input, status reporting, and interrupt generation. serial control port the serial control port (scp) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other scp bus-compatible serial devices. the scp is a slave device to the opb bus, and supports a three-wire interface to the serial port (receive, transmit, and clock). it provides a glueless serial interface to many microcontrollers, with clock inversion and reverse data. the port includes a program- mable clock rate divider (sysclk/4 to sysclk/1024), and bit rate is supported up to 1/4 the frequency of the system clock. general purpose i/o controller the general purpose i/o (gpio) controller enables the multiplexing of module i/os, with functions that include programmable open-drain output conversion, registered input and output functions, and simplified gpio definition.
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 16 of 54 stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information pinout diagram ac ab aa y w v u t r p n m l k j h g f e d c b a v dd25 ground i/o pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 v dd33 legend:
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 17 of 54 signal pins sorted by signal name signal grid (pin) position group signal grid (pin) position group aud_vdda0 n22 pll analog pwr + gnd bi_data2 ab15 bus interface aud_vdda1 k20 pll analog pwr + gnd bi_data3 ab16 bus interface bi_address8 (msb) aa2 bus interface bi_data4 ab17 bus interface bi_address9 ac3 bus interface bi_data5 aa16 bus interface bi_address10 ac4 bus interface bi_data6 aa15 bus interface bi_address11 ab5 bus interface bi_data7 ac14 bus interface bi_address12 ac5 bus interface bi_data8 y14 bus interface bi_address13 aa5 bus interface bi_data9 ac15 bus interface bi_address14 ab9 bus interface bi_data10 ac16 bus interface bi_address15 aa9 bus interface bi_data11 ac17 bus interface bi_address16 ac8 bus interface bi_data12 y17 bus interface bi_address17 ab8 bus interface bi_data13 y16 bus interface bi_address18 ac7 bus interface bi_data14 ab14 bus interface bi_address19 ab7 bus interface bi_data15 (lsb) ab13 bus interface bi_address20 ac6 bus interface bi_oe ac13 bus interface bi_address21 ab6 bus interface bi_ready aa10 bus interface bi_address22 ab4 bus interface bi_r w ab10 bus interface bi_address23 y6 bus interface bi_wbe0 y11 bus interface bi_address24 aa6 bus interface ci_clock u20 channel interface bi_address25 y7 bus interface ci_data0 (msb) y23 channel interface bi_address26 aa7 bus interface ci_data1 y22 channel interface bi_address27 y8 bus interface ci_data2 w23 channel interface bi_address28 aa8 bus interface ci_data3 w21 channel interface bi_address29 y10 bus interface ci_data4 w22 channel interface bi_address30 ac9 bus interface ci_data5 v20 channel interface bi_address31 (lsb)/bi_wbe1 ac10 bus interface ci_data6 v23 channel interface bi_cs0 y13 bus interface ci_data7 (lsb) v21 channel interface bi_cs1 ab12 bus interface ci_data_enable v22 channel interface bi_cs2 aa12 bus interface clk_vdda c9 pll analog pwr + gnd bi_cs3 ac12 bus interface dac1_agnd0 l1 dac analog pwr + gnd bi_data0 (msb) aa13 bus interface dac1_agnd1 j1 dac analog pwr + gnd bi_data1 aa14 bus interface dac1_agnd2 g3 dac analog pwr + gnd
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 18 of 54 stb03_sds_0323.fm.00 march 23, 2000 dac1_avdd0 l3 dac analog pwr + gnd da_serial_data0 v4 audio dac1_avdd1 k2 dac analog pwr + gnd dv1_data0 (msb) e3 video and graphics dac1_avdd2 j3 dac analog pwr + gnd dv1_data1 e2 video and graphics dac1_avdd3 g2 dac analog pwr + gnd dv1_data2 e1 video and graphics dac1_bout h4 video and graphics dv1_data3 d2 video and graphics dac1_bref_out f1 video and graphics dv1_data4 d1 video and graphics dac1_gout k3 video and graphics dv1_data5 c2 video and graphics dac1_gref_out l4 video and graphics dv1_data6 c1 video and graphics dac1_rout l2 video and graphics dv1_data7 (lsb) b3 video and graphics dac1_rref_out h3 video and graphics dv1_hsync f2 video and graphics dac1_vref_in h2 video and graphics dv1_pixel_clock f4 video and graphics dac2_agnd0 m2 dac analog pwr + gnd dv1_vsync f3 video and graphics dac2_agnd1 p3 dac analog pwr + gnd edmac3_ack/ide_ack y2 direct memory access dac2_agnd2 u1 dac analog pwr + gnd edmac3_req/ide_req aa1 direct memory access dac2_avdd0 m1 dac analog pwr + gnd gnd b1 ground dac2_avdd1 n4 dac analog pwr + gnd gnd b2 ground dac2_avdd2 p4 dac analog pwr + gnd gnd b22 ground dac2_avdd3 t2 dac analog pwr + gnd gnd b23 ground dac2_bout t3 video and graphics gnd c21 ground dac2_bref_out u2 video and graphics gnd d4 ground dac2_gout n3 video and graphics gnd d20 ground dac2_gref_out n1 video and graphics gnd y4 ground dac2_rout m3 video and graphics gnd y20 ground dac2_rref_out t1 video and graphics gnd aa3 ground dac2_vref_in r3 video and graphics gnd aa21 ground da_bit_clock v1 audio gnd ab1 ground da_iec_958 w1 audio gnd ab2 ground da_lr_channel_clock v3 audio gnd ab22 ground da_oversampling_clo ck v2 audio gnd ab23 ground signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 19 of 54 gnd ac1 ground gpio_22 r2 general purpose i/o gnd ac2 ground gpio_23 r1 general purpose i/o gnd ac22 ground gpio_24 p2 general purpose i/o gnd ac23 ground gpio_25 p1 general purpose i/o gnd a1 ground gpio_26 n2 general purpose i/o gnd a2 ground gpio_27 k4 general purpose i/o gnd a22 ground gpio_28 k1 general purpose i/o gnd a23 ground gpio_29 c6 general purpose i/o gnd c3 ground gpio_30 g23 general purpose i/o gnd d12 ground gpio_31 g21 general purpose i/o gnd m20 ground g_system_clock c8 global gnd y12 ground g_system_rst c7 global gnd m4 ground i2c0_scl u4 inter-integrated circuit (iic) gpio_0 n23 general purpose i/o i2c0_sda u3 inter-integrated circuit (iic) gpio_1 n21 general purpose i/o int0 aa17 interrupt gpio_2 g4 general purpose i/o int1 ab3 interrupt gpio_3 ac11 general purpose i/o int2 j23 interrupt gpio_4 a15 general purpose i/o int3 k22 interrupt gpio_5 h20 general purpose i/o mux0_0 k23 multiplexed i/o gpio_6 aa18 general purpose i/o mux0_1 k21 multiplexed i/o gpio_7 ac18 general purpose i/o mux0_2 j21 multiplexed i/o gpio_8 ab20 general purpose i/o mux0_3 l23 multiplexed i/o gpio_9 b7 general purpose i/o mux0_4 l22 multiplexed i/o gpio_10 a7 general purpose i/o mux0_5 l21 multiplexed i/o gpio_11 d7 general purpose i/o mux0_6 l20 multiplexed i/o gpio_12 b8 general purpose i/o mux0_7 m21 multiplexed i/o gpio_13 a8 general purpose i/o mux0_8 n20 multiplexed i/o gpio_14 d8 general purpose i/o mux0_9 p21 multiplexed i/o gpio_15 b9 general purpose i/o mux0_10 p22 multiplexed i/o gpio_16 ab11 general purpose i/o mux0_11 p23 multiplexed i/o gpio_17 aa11 general purpose i/o mux0_12 m22 multiplexed i/o gpio_18 g1 general purpose i/o mux0_13 m23 multiplexed i/o gpio_19 h1 general purpose i/o mux0_14 j22 multiplexed i/o gpio_20 j2 general purpose i/o mux0_15 h21 multiplexed i/o gpio_21 t4 general purpose i/o mux0_16 h23 multiplexed i/o signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 20 of 54 stb03_sds_0323.fm.00 march 23, 2000 mux0_17 g20 multiplexed i/o reserved - tie to 3.3 v b6 global mux0_18 b20 multiplexed i/o sc0_clk ab21 smart card interface 0 mux0_19 a21 multiplexed i/o sc0_detect y18 smart card interface 0 mux0_20 c23 multiplexed i/o sc0_io ac21 smart card interface 0 mux0_21 d23 multiplexed i/o sc0_reset aa23 smart card interface 0 mux0_22 e21 multiplexed i/o sc0_vcc_command aa22 smart card interface 0 mux0_23 f21 multiplexed i/o sc1_clk aa19 smart card interface 1 mux0_24 f23 multiplexed i/o sc1_detect ab18 smart card interface 1 mux0_25 g22 multiplexed i/o sc1_io ac19 smart card interface 1 mux0_26 f20 multiplexed i/o sc1_reset ab19 smart card interface 1 mux0_27 f22 multiplexed i/o sc1_vcc_command ac20 smart card interface 1 mux0_28 e23 multiplexed i/o sd1_address0 (msb) c16 sdram1 controller mux0_29 e22 multiplexed i/o sd1_address1 a17 sdram1 controller mux0_30 d22 multiplexed i/o sd1_address2 b16 sdram1 controller mux0_31 c22 multiplexed i/o sd1_address3 b17 sdram1 controller mux0_32 b21 multiplexed i/o sd1_address4 d16 sdram1 controller mux0_33 a20 multiplexed i/o sd1_address5 c17 sdram1 controller mux0_34 h22 multiplexed i/o sd1_address6 d17 sdram1 controller mux1_0 y1 multiplexed i/o sd1_address7 c18 sdram1 controller mux1_1 w2 multiplexed i/o sd1_address8 d18 sdram1 controller mux1_2 w3 multiplexed i/o sd1_address9 c19 sdram1 controller mux2_0 a3 multiplexed i/o sd1_address10 b19 sdram1 controller mux2_1 b4 multiplexed i/o sd1_address11 a19 sdram1 controller mux2_2 a4 multiplexed i/o sd1_address12 b18 sdram1 controller mux2_3 b5 multiplexed i/o sd1_address13 (lsb) a18 sdram1 controller mux3_0 u23 multiplexed i/o sd1_cas b15 sdram1 controller mux3_1 u21 multiplexed i/o sd1_clk d14 sdram1 controller mux3_2 u22 multiplexed i/o sd1_cs0 a16 sdram1 controller mux3_3 t20 multiplexed i/o sd1_data0 (msb) d10 sdram1 controller mux3_4 t23 multiplexed i/o sd1_data1 b10 sdram1 controller mux3_5 t21 multiplexed i/o sd1_data2 d11 sdram1 controller mux3_6 t22 multiplexed i/o sd1_data3 b11 sdram1 controller mux3_7 r23 multiplexed i/o sd1_data4 c12 sdram1 controller mux3_8 r21 multiplexed i/o sd1_data5 a12 sdram1 controller mux3_9 r22 multiplexed i/o sd1_data6 c13 sdram1 controller mux3_10 p20 multiplexed i/o sd1_data7 d13 sdram1 controller signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 21 of 54 sd1_data8 a13 sdram1 controller vdd25 d3 2.5 v power sd1_data9 b13 sdram1 controller vdd25 d5 2.5 v power sd1_data10 b12 sdram1 controller vdd25 d19 2.5 v power sd1_data11 a11 sdram1 controller vdd25 d21 2.5 v power sd1_data12 c11 sdram1 controller vdd25 e4 2.5 v power sd1_data13 a10 sdram1 controller vdd25 e20 2.5 v power sd1_data14 c10 sdram1 controller vdd25 w4 2.5 v power sd1_data15 (lsb) a9 sdram1 controller vdd25 w20 2.5 v power sd1_dqmh c14 sdram1 controller vdd25 y3 2.5 v power sd1_dqml b14 sdram1 controller vdd25 y5 2.5 v power sd1_ras c15 sdram1 controller vdd25 y19 2.5 v power sd1_we a14 sdram1 controller vdd25 y21 2.5 v power serial1/infrared_cts a6 serial1 / infrared vdd33 d9 3.3 v power serial1/infrared_rts d6 serial1 / infrared vdd33 d15 3.3 v power serial1/infrared_rxd a5 serial1 / infrared vdd33 j4 3.3 v power serial1/infrared_txd c5 serial1 / infrared vdd33 j20 3.3 v power vdd25 aa4 2.5 v power vdd33 r4 3.3 v power vdd25 aa20 2.5 v power vdd33 r20 3.3 v power vdd25 c4 2.5 v power vdd33 y9 3.3 v power vdd25 c20 2.5 v power vdd33 y15 3.3 v power signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 22 of 54 stb03_sds_0323.fm.00 march 23, 2000 . signal pins sorted by pin number grid (pin) position signal group grid (pin) position signal group a1 gnd ground aa13 bi_data0 (msb) bus interface a2 gnd ground aa14 bi_data1 bus interface a3 mux2_0 multiplexed i/o aa15 bi_data6 bus interface a4 mux2_2 multiplexed i/o aa16 bi_data5 bus interface a5 serial1/infrared_rxd serial1 / infrared aa17 int0 interrupt a6 serial1/infrared_cts serial1 / infrared aa18 gpio_6 general purpose i/o a7 gpio_10 general purpose i/o aa19 sc1_clk smart card interface 1 a8 gpio_13 general purpose i/o aa20 vdd25 2.5 v power a9 sd1_data15 (lsb) sdram1 controller aa21 gnd ground a10 sd1_data13 sdram1 controller aa22 sc0_vcc_command smart card interface 0 a11 sd1_data11 sdram1 controller aa23 sc0_reset smart card interface 0 a12 sd1_data5 sdram1 controller ab1 gnd ground a13 sd1_data8 sdram1 controller ab2 gnd ground a14 sd1_we sdram1 controller ab3 int1 interrupt a15 gpio_4 general purpose i/o ab4 bi_address22 bus interface a16 sd1_cs0 sdram1 controller ab5 bi_address11 bus interface a17 sd1_address1 sdram1 controller ab6 bi_address21 bus interface a18 sd1_address13 (lsb) sdram1 controller ab7 bi_address19 bus interface a19 sd1_address11 sdram1 controller ab8 bi_address17 bus interface a20 mux0_33 multiplexed i/o ab9 bi_address14 bus interface a21 mux0_19 multiplexed i/o ab10 bi_r w bus interface a22 gnd ground ab11 gpio_16 general purpose i/o a23 gnd ground ab12 bi_cs1 bus interface aa1 edmac3_req/ide_req direct memory access ab13 bi_data15 (lsb) bus interface aa2 bi_address8 (msb) bus interface ab14 bi_data14 bus interface aa3 gnd ground ab15 bi_data2 bus interface aa4 vdd25 2.5 v power ab16 bi_data3 bus interface aa5 bi_address13 bus interface ab17 bi_data4 bus interface aa6 bi_address24 bus interface ab18 sc1_detect smart card interface 1 aa7 bi_address26 bus interface ab19 sc1_reset smart card interface 1 aa8 bi_address28 bus interface ab20 gpio_8 general purpose i/o aa9 bi_address15 bus interface ab21 sc0_clk smart card interface 0 aa10 bi_ready bus interface ab22 gnd ground aa11 gpio_17 general purpose i/o ab23 gnd ground aa12 bi_cs2 bus interface ac1 gnd ground
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 23 of 54 ac2 gnd ground b15 sd1_cas sdram1 controller ac3 bi_address9 bus interface b16 sd1_address2 sdram1 controller ac4 bi_address10 bus interface b17 sd1_address3 sdram1 controller ac5 bi_address12 bus interface b18 sd1_address12 sdram1 controller ac6 bi_address20 bus interface b19 sd1_address10 sdram1 controller ac7 bi_address18 bus interface b20 mux0_18 multiplexed i/o ac8 bi_address16 bus interface b21 mux0_32 multiplexed i/o ac9 bi_address30 bus interface b22 gnd ground ac10 bi_address31 (lsb)/bi_web1 bus interface b23 gnd ground ac11 gpio_3 general purpose i/o c1 dv1_data6 video and graphics ac12 bi_cs3 bus interface c2 dv1_data5 video and graphics ac13 bi_oe bus interface c3 gnd ground ac14 bi_data7 bus interface c4 vdd25 2.5 v power ac15 bi_data9 bus interface c5 serial1/infrared_txd serial1 / infrared ac16 bi_data10 bus interface c6 gpio_29 general purpose i/o ac17 bi_data11 bus interface c7 g_system_rst global ac18 gpio_7 general purpose i/o c8 g_system_clock global ac19 sc1_io smart card interface 1 c9 clk_vdda pll analog pwr + gnd ac20 sc1_vcc_command smart card interface 1 c10 sd1_data14 sdram1 controller ac21 sc0_io smart card interface 0 c11 sd1_data12 sdram1 controller ac22 gnd ground c12 sd1_data4 sdram1 controller ac23 gnd ground c13 sd1_data6 sdram1 controller b1 gnd ground c14 sd1_dqmh sdram1 controller b2 gnd ground c15 sd1_ras sdram1 controller b3 dv1_data7 (lsb) video and graphics c16 sd1_address0 (msb) sdram1 controller b4 mux2_1 multiplexed i/o c17 sd1_address5 sdram1 controller b5 mux2_3 multiplexed i/o c18 sd1_address7 sdram1 controller b6 reserved - tie to 3.3 v global c19 sd1_address9 sdram1 controller b7 gpio_9 general purpose i/o c20 vdd25 2.5 v power b8 gpio_12 general purpose i/o c21 gnd ground b9 gpio_15 general purpose i/o c22 mux0_31 multiplexed i/o b10 sd1_data1 sdram1 controller c23 mux0_20 multiplexed i/o b11 sd1_data3 sdram1 controller d1 dv1_data4 video and graphics b12 sd1_data10 sdram1 controller d2 dv1_data3 video and graphics b13 sd1_data9 sdram1 controller d3 vdd25 2.5 v power b14 sd1_dqml sdram1 controller d4 gnd ground signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 24 of 54 stb03_sds_0323.fm.00 march 23, 2000 d5 vdd25 2.5 v power g2 dac1_avdd3 dac analog pwr + gnd d6 serial1/infrared_rts serial1 / infrared g3 dac1_agnd2 dac analog pwr + gnd d7 gpio_11 general purpose i/o g4 gpio_2 general purpose i/o d8 gpio_14 general purpose i/o g20 mux0_17 multiplexed i/o d9 vdd33 3.3 v power g21 gpio_31 general purpose i/o d10 sd1_data0 (msb) sdram1 controller g22 mux0_25 multiplexed i/o d11 sd1_data2 sdram1 controller g23 gpio_30 general purpose i/o d12 gnd ground h1 gpio_19 general purpose i/o d13 sd1_data7 sdram1 controller h2 dac1_vref_in video and graphics d14 sd1_clk sdram1 controller h3 dac1_rref_out video and graphics d15 vdd33 3.3 v power h4 dac1_bout video and graphics d16 sd1_address4 sdram1 controller h20 gpio_5 general purpose i/o d17 sd1_address6 sdram1 controller h21 mux0_15 multiplexed i/o d18 sd1_address8 sdram1 controller h22 mux0_34 multiplexed i/o d19 vdd25 2.5 v power h23 mux0_16 multiplexed i/o d20 gnd ground j1 dac1_agnd1 dac analog pwr + gnd d21 vdd25 2.5 v power j2 gpio_20 general purpose i/o d22 mux0_30 multiplexed i/o j3 dac1_avdd2 dac analog pwr + gnd d23 mux0_21 multiplexed i/o j4 vdd33 3.3 v power e1 dv1_data2 video and graphics j20 vdd33 3.3 v power e2 dv1_data1 video and graphics j21 mux0_2 multiplexed i/o e3 dv1_data0 (msb) video and graphics j22 mux0_14 multiplexed i/o e4 vdd25 2.5 v power j23 int2 interrupt e20 vdd25 2.5 v power k1 gpio_28 general purpose i/o e21 mux0_22 multiplexed i/o k2 dac1_avdd1 dac analog pwr + gnd e22 mux0_29 multiplexed i/o k3 dac1_gout video and graphics e23 mux0_28 multiplexed i/o k4 gpio_27 general purpose i/o f1 dac1_bref_out video and graphics k20 aud_vdda1 pll analog pwr + gnd f2 dv1_hsync video and graphics k21 mux0_1 multiplexed i/o f3 dv1_vsync video and graphics k22 int3 interrupt f4 dv1_pixel_clock video and graphics k23 mux0_0 multiplexed i/o f20 mux0_26 multiplexed i/o l1 dac1_agnd0 dac analog pwr + gnd f21 mux0_23 multiplexed i/o l2 dac1_rout video and graphics f22 mux0_27 multiplexed i/o l3 dac1_avdd0 dac analog pwr + gnd f23 mux0_24 multiplexed i/o l4 dac1_gref_out video and graphics g1 gpio_18 general purpose i/o l20 mux0_6 multiplexed i/o signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 25 of 54 l21 mux0_5 multiplexed i/o t1 dac2_rref_out video and graphics l22 mux0_4 multiplexed i/o t2 dac2_avdd3 dac analog pwr + gnd l23 mux0_3 multiplexed i/o t3 dac2_bout video and graphics m1 dac2_avdd0 dac analog pwr + gnd t4 gpio_21 general purpose i/o m2 dac2_agnd0 dac analog pwr + gnd t20 mux3_3 multiplexed i/o m3 dac2_rout video and graphics t21 mux3_5 multiplexed i/o m4 gnd ground t22 mux3_6 multiplexed i/o m20 gnd ground t23 mux3_4 multiplexed i/o m21 mux0_7 multiplexed i/o u1 dac2_agnd2 dac analog pwr + gnd m22 mux0_12 multiplexed i/o u2 dac2_bref_out video and graphics m23 mux0_13 multiplexed i/o u3 i2c0_sda inter-integrated circuit (iic) n1 dac2_gref_out video and graphics u4 i2c0_scl inter-integrated circuit (iic) n2 gpio_26 general purpose i/o u20 ci_clock channel interface n3 dac2_gout video and graphics u21 mux3_1 multiplexed i/o n4 dac2_avdd1 dac analog pwr + gnd u22 mux3_2 multiplexed i/o n20 mux0_8 multiplexed i/o u23 mux3_0 multiplexed i/o n21 gpio_1 general purpose i/o v1 da_bit_clock audio n22 aud_vdda0 pll analog pwr + gnd v2 da_oversampling_clo ck audio n23 gpio_0 general purpose i/o v3 da_lr_channel_clock audio p1 gpio_25 general purpose i/o v4 da_serial_data0 audio p2 gpio_24 general purpose i/o v20 ci_data5 channel interface p3 dac2_agnd1 dac analog pwr + gnd v21 ci_data7 (lsb) channel interface p4 dac2_avdd2 dac analog pwr + gnd v22 ci_data_enable channel interface p20 mux3_10 multiplexed i/o v23 ci_data6 channel interface p21 mux0_9 multiplexed i/o w1 da_iec_958 audio p22 mux0_10 multiplexed i/o w2 mux1_1 multiplexed i/o p23 mux0_11 multiplexed i/o w3 mux1_2 multiplexed i/o r1 gpio_23 general purpose i/o w4 vdd25 2.5 v power r2 gpio_22 general purpose i/o w20 vdd25 2.5 v power r3 dac2_vref_in video and graphics w21 ci_data3 channel interface r4 vdd33 3.3 v power w22 ci_data4 channel interface r20 vdd33 3.3 v power w23 ci_data2 channel interface r21 mux3_8 multiplexed i/o y1 mux1_0 multiplexed i/o r22 mux3_9 multiplexed i/o y2 edmac3_ack/ide_ack direct memory access r23 mux3_7 multiplexed i/o y3 vdd25 2.5 v power signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 26 of 54 stb03_sds_0323.fm.00 march 23, 2000 y4 gnd ground y14 bi_data8 bus interface y5 vdd25 2.5 v power y15 vdd33 3.3 v power y6 bi_address23 bus interface y16 bi_data13 bus interface y7 bi_address25 bus interface y17 bi_data12 bus interface y8 bi_address27 bus interface y18 sc0_detect smart card interface 0 y9 vdd33 3.3 v power y19 vdd25 2.5 v power y10 bi_address29 bus interface y20 gnd ground y11 bi_wbe0 bus interface y21 vdd25 2.5 v power y12 gnd ground y22 ci_data1 channel interface y13 bi_cs0 bus interface y23 ci_data0 (msb) channel interface signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 27 of 54 stb03xxx multiplexed i/o signal table stb03xxx has four sets of multiplexed i/o signals: mux0, mux1, mux2, and mux3. at reset, the multiplexed i/o signals are tristated, unless noted. the muxtiplexed i/o can be selected by column in the following tables. for example, if input/output 1 is selected, input/output 2 and input/output 3 are not available. blank entries indicate reserved multiplexing. multiplexed i/o signal table bit # input/output 1 i/o input/output 2 i/o 00 sd0_address0 (msb) o ieee1284_pd0 (msb) i/o 01 sd0_address1 o ieee1284_pd1 i/o 02 sd0_address2 o ieee1284_pd2 i/o 03 sd0_address3 o ieee1284_pd3 i/o 04 sd0_address4 o ieee1284_pd4 i/o 05 sd0_address5 o ieee1284_pd5 i/o 06 sd0_address6 o ieee1284_pd6 i/o 07 sd0_address7 o ieee1284_pd7 i/o 08 sd0_address8 o ieee1284_autofeed i/o 09 sd0_address9 o ieee1284_select_in i/o 10 sd0_address10 o ieee1284_busy i/o 11 sd0_address11 o ieee1284_select i/o 12 sd0_address12 o ieee1284_pe i/o 13 sd0_address13 o ieee1284_error i/o 14 sd0_cs0 o ieee1284_ack i/o 15 sd0_ras o ieee1284_pdir o 16 sd0_cas o ieee1284_init i/o 17 sd0_we o ieee1284_strobe i/o 18 sd0_data0 i/o bi_data16 i/o 19 sd0_data1 i/o bi_data17 i/o 20 sd0_data2 i/o bi_data18 i/o 21 sd0_data3 i/o bi_data19 i/o 22 sd0_data4 i/o bi_data20 i/o 23 sd0_data5 i/o bi_data21 i/o 24 sd0_data6 i/o bi_data22 i/o 25 sd0_data7 i/o bi_data23 i/o 26 sd0_data8 i/o bi_data24 i/o 27 sd0_data9 i/o bi_data25 i/o 28 sd0_data10 i/o bi_data26 i/o
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 28 of 54 stb03_sds_0323.fm.00 march 23, 2000 29 sd0_data11 i/o bi_data27 i/o 30 sd0_data12 i/o bi_data28 i/o 31 sd0_data13 i/o bi_data29 i/o 32 sd0_data14 i/o bi_data30 i/o 33 sd0_data15 i/o bi_data31 (lsb) i/o 34 sd0_clk o ieee1284_host o multiplexed i/o signal table - mux1 bit # input/output 1 i/o input/output 2 i/o 00 edmac2_ack o ebm_holdack i/o 01 edmac2_req i ebm_holdreq i/o 02 edmac2_eot i/o ebm_busreq i/o multiplexed i/o signal table - mux2 bit # input/output 1 i/o input/output 2 i/o 00 serial0/16550_txd o ssp_txd o 01 serial0/16550_rxd i ssp_rxd i 02 serial0/16550_cts i ssp_clk i 03 serial0/16550_rts o ssp_fs i/o multiplexed i/o signal table - mux3 bit # input/output 1 i/o input/output 2 i/o input/output 3 i/o input/output 4 i/o 00 hsp_data0 o ieee1284_pd0 (msb) i/o serial1/infrare d_dsr (through gpio bit 31 alt rcv 2) i rt_ts1e o 01 hsp_data1 o ieee1284_pd1 i/o serial1/infrare d_dtr o rt_ts2e o 02 hsp_data2 o ieee1284_pd2 i/o rw_tms (through gpio bit 11 alt rcv 1 i rt_ts1o o 03 hsp_data3 o ieee1284_pd3 i/o rw_tdi (through gpio bit 12 alt rcv 1) i rt_ts2o o 04 hsp_data4 o ieee1284_pd4 i/o rw_tck (through gpio bit 13 alt rcv 1) i rt_ts3 o multiplexed i/o signal table (continued) bit # input/output 1 i/o input/output 2 i/o
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 29 of 54 05 hsp_data5 o ieee1284_pd5 i/o rw_tdo o rt_ts4 o 06 hsp_data6 o ieee1284_pd6 i/o rw_halt (through gpio bit 15 alt rcv 1) i rt_ts5 o 07 hsp_data7 o ieee1284_pd7 i/o serial0/16550_ds r (through gpio bit 5 alt rcv 3) i rt_ts6 o 08 hsp_clock o ieee1284_ strobe i/o serial0/16550_dt r o rt_clk o 09 hsp_data_ enable o ieee1284_ack i/o serial0/16550_dc d (through gpio bit 6 alt rcv 3) i 10 hsp_packet_ start o ieee1284_init i/o serial0/16550_ri (through gpio bit 8 alt rcv 3) i multiplexed i/o signal table - mux3 (continued) bit # input/output 1 i/o input/output 2 i/o input/output 3 i/o input/output 4 i/o
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary pin and i/o information page 30 of 54 stb03_sds_0323.fm.00 march 23, 2000 general purpose i/o (gpio) the following table describes the gpio bits. for each gpio bit only one signal can be selected at a time. each table row lists the signal associated with each logical gpio bit number. the ?rst column lists the gpio bit number. the second column lists the signal connected as input or output to the ?rst alternate gpio multiplexer. the signal name is listed ?rst, followed by the signal description. the third column gives the direction of the signal listed in column 2. the same format is used for columns 4 through 7. blank entries indicate reserved gpio multiplexing. gpio bit number refers to the device gpio signal name, not the physical device pin number. after reset all gpios are programmed as inputs, with the exception of gpio0 bit 29 (pwm output), which defaults to an open-drain output, and gpio bit 14 (jtag tdo output), which defaults to an output (if bi_data[4] is set to 0 during reset). general purpose i/o bits bit # input/output mux 1 i/o input/output mux 2 i/o input/output mux 3 i/o 00 i2c1_scl i/o da_deemphasis0 o da_surmod0 o 01 i2c1_sda i/o da_deemphasis1 o da_surmod1 o 02 av_csync bi_cs4 i o gpt_freqgenout o da_surmod0 int4 o i 03 sys_clk o bi_cs5 o da_surmod1 int5 o i 04 edma c0_req i sd1_cs1 o serial0/16550_dtr o 05 edma c0_a ck o sd0_cs1 o serial0/16550_dsr i 06 scp_txd o ci_packet_start i serial0/16550_dcd i 07 scp_rxd i ci_data_error i ts_bclken i 08 scp_clk o ts_req o serial0/16550_ri i 09 pwm0 o gpt_comp0 o gpt_capt0 i o 10 pwm1 o gpt_comp1 o gpt_capt1 bi_cs7 i o 11 rw_tms i ssp_txd o bi_cs6 o 12 rw_tdi i ssp_rxd i bi_cs7 o 13 rw_tck i ssp_clk i int6 i 14 rw_tdo o ssp_fs i/o int7 i 15 r w_hal t i serial0/16550_clk - external serial0/16550 clock input i sys_clk o 16 da_serial_data1 o bi_cs4 o 17 da_serial_data2 o bi_cs5 o hsp_error o 18 dv_transparency_ gate i/o dv2_pixel_clock i serial1/infrared_clk - external serial1/infrared clock input i
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 pin and i/o information page 31 of 54 19 ttx_req i/o dv2_vsync i/o 20 ttx_data i/o dv2_hsync i/o 21 dv2_data0 (msb) i/o ieee1284_a ut ofeed i/o int8 i 22 dv2_data1 i/o ieee1284_select_in i/o int9 i 23 dv2_data2 i/o ieee1284_busy i/o 24 dv2_data3 i/o ieee1284_select i/o 25 dv2_data4 i/o ieee1284_pe i/o 26 dv2_data5 i/o ieee1284_err or i/o 27 dv2_data6 i/o ieee1284_pdir o 28 dv2_data7 i/o ieee1284_host o 29 denc_pwm_output o xpt_pwm_output o 30 edma c1_req bi_wbe2 i o serial1/infrared_dtr o sd0_dqmh o 31 edma c1_a ck o serial1/infrared_dsr bi_wbe3 i o sd0_dqml o general purpose i/o bits (continued) bit # input/output mux 1 i/o input/output mux 2 i/o input/output mux 3 i/o
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 32 of 54 stb03_sds_0323.fm.00 march 23, 2000 electrical information the following tables give the absolute ratings for various electrical characteristics. drivers/receivers four types of i/o drivers and receivers are used on the stb03xxx device, as follows: . dc electrical characteristics the table, dc electrical characteristics, gives the absolute ratings for various electrical characteristics. the temperature is 70 c in all cases. i/o driver types driver/ receiver type characteristics used on i/o signals: bp3365 5 v tolerant, no pull-up or pull-down (external pull-up is required) g_system_reset, gpio[2], gpio[29], sc0_io, sc0_clk, sc0_detect, sc0_reset, sc0_vcc_command, sc1_io, sc1_clk, sc1_detect, sc1_reset, sc1_vcc_command, bi_ready bp3335 5 v tolerant, no pull-up or pull-down (external pull-up is required) i2c0_sda, i2c0_scl, gpio[0], gpio[1] bt3350pu 3.3 v i/o with pull-up bi_data[0:15], mux0[18:33] bt3365pu 3.3 v i/o with pull-up all other digital i/o signals dc electrical characteristics driver / receiver symbol parameter conditions min typ max units bp3335 v ih high level input voltage 2.00 5.50 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 17.0 ma 2.40 v v ol low level output voltage v cc = min, i ol = 11.0 ma 0.4 v bp3365 v ih high level input voltage 2.00 5.50 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 9.0 ma 2.40 v v ol low level output voltagec v cc = min, i ol = 6.0 ma 0.4 v 1. maximum v ih applies to overshoot only. 2. minimum v il applies to undershoot only.
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 33 of 54 bt3350pu v ih high level input voltage 2.00 4.0 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 12.0 ma 2.40 v v ol low level output voltage v cc = min, i ol = 8.0 ma 0.4 v bt3365pu v ih high level input voltage 2.00 4.0 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 9.0 ma 2.40 v v ol low level output voltage v cc = min, i ol = 6.0 ma 0.4 v bt3350pu, bt3365pu i i maximum input current v in = 0 v -250 m a bp3335, bp3365 i i maximum input current 0 m a n/a i cc supply current, 2.5 v v cc = max tbd ma n/a i cc330 supply current, 3.3 v v cc330 = max tbd ma all c i input capacitance v cc = nom, v i = nom 2.6 pf all esd electro static discharge -3000 3000 v n/a pd power dissipation 2.5 w dc electrical characteristics (continued) driver / receiver symbol parameter conditions min typ max units 1. maximum v ih applies to overshoot only. 2. minimum v il applies to undershoot only.
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 34 of 54 stb03_sds_0323.fm.00 march 23, 2000 the absolute maximum ratings in the following table are stress ratings only. operation at or beyond these maximum ratings may cause permanent damage to the device. . operating conditions the stb03xxx digital set-top box integrated controller can interface to either 3.3 v or 5 v technologies. 5 v interfaces are supported only for drivers/receivers supporting 5 v tolerance (see drivers/receivers ). the range for supply voltages is specified for five-percent margins relative to a nominal 2.5 v and 3.3 v power supply. note: device operation beyond the conditions specified in the table below is not recommended. extended operation beyond the recommended conditions may affect device reliability. power considerations power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. power sequencing the 2.5 v power supply must maintain the following relationship whenever the 3.3 v power supply voltage is greater than 0.4 v: 2.5 v power supply voltage >= 0.4 v supply excursions outside this range must be limited to less than 25 ms duration during each power-up or power-down event. general recommendation system designs that derive the 2.5 v supply from a regulator running from the 3.3 v supply are recom- mended to ensure a fixed relationship between the two voltage supplies. such usage substantially reduces the potential for the 3.3 v supply to be present without the 2.5 v supply. absolute maximum ratings parameter maximum rating supply voltage with respect to gnd, 2.5 v supply 3.0 v supply voltage with respect to gnd, 3.3 v supply 3.9 v case temperature under bias tbd storage temperature -65 c to 150 c recommended operating conditions symbol parameter min max unit v cc supply voltage, 2.5 v 2.38 2.62 v v cc330 supply voltage, 3.3 v 3.14 3.47 v t a operating free air temperature 0 70 c
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 35 of 54 recommended connections power and ground pins should all be connected to separate power and ground planes in the circuit board to which the stb03xxx is mounted. unused input pins must be tied inactive, either high or low. recommended connections for analog i/o pins dac1_avdd0 dac1_avdd1 dac1_avdd2 dac1_avdd3 dac2_avdd0 dac2_avdd1 dac2_avdd2 dac2_avdd3 dac1_gref_out dac2_gref_out dac1_rref_out dac2_rref_out dac1_bref_out dac2_bref_out clk_vdda aud_vdda0 aud_vdda1 .1 mf l3 j3 k2 g2 m1 p4 n4 t2 .1 mf .1 mf .1 mf .1 mf 22 mf 784 .1 mf .1 mf 5 k 1.2 mh 2.5 v 1.2 mf 2.5v 1 nh 2.5 v l4 n1 c9 f1 (for a 75 w dac output load) 1 nf 1 nf 784 h3 t1 1 nf 1 nf u2 n22 k20
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 36 of 54 stb03_sds_0323.fm.00 march 23, 2000 i/o timing diagrams ac speci?cation note 1. clock timing and switching characters are speci?ed in accordance with operating conditions in recommended operating conditions on page 34. ac speci?cations assume a 30 pf output load. all input slow rates must be 5 ns or less, unless otherwise speci?ed (rise and fall times measured between 0.8 v and 2.0 v). also, all input clocks must have a 40C60% duty cycle, unless otherwise speci?ed. note 2. the internal sysclk is shown in the diagrams to indicate the relationship of the number of cycles between various signal edges on the timing diagram. note 3. where multiple interfaces share the same timing diagram, the signals names are listed using an n to indicate that the timings apply to both interfaces. for example, the sd0 and sd1 interface signal names in the sdram interface timing diagram are listed as sdn. g_sysclk timing sysclk timing values note 1. cycle-to-cycle jitter allowed between any two edges. note 2. rise and fall times measured between 0.8 v and 2.0 v. symbol parameter min max units f c sysclk clock input frequency (nominal 27) mhz t cs clock edge stability 1 0.15 ns t ch clock input high time 15 ns t cl clock input low time 15 ns t cr clock input rise time 2 0.6 ns t cf clock input fall time 2 0.6 ns tcr tcf tcl tch tc 2.0 v 1.5 v 0.8 v
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 37 of 54 g_system_reset timing g_system_reset timing values note: external logic must drive g_system_reset low during power-on, using an open-drain driver . symbol parameter min max units t 1 clock to reset inactive 152 m s t 2 input setup time 0 ns t 3 input hold time 80 ns t 4 input rise time 37 ns t 5 input fall time 37 ns valid t1 v dd g_system_clock g_system_reset t4 t5 2.0 v 0.8 v power-on timing edge timing g_system_reset input input input valid input con?guration pins (bi_data[0:7], mux2[0]) t2 t3
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 38 of 54 stb03_sds_0323.fm.00 march 23, 2000 sram interface timing sram interface timing values symbol parameter min max units t 1 at sysclk = 54 mhz 19.25 ns t 2 address output valid time 12 ns t 3 address output hold time 3 ns t 4 chip select output valid time 12 ns t 5 chip select output hold time 3 ns t 6 output enable output valid time 12 ns t 7 output enable output hold time 3 ns t 8 write byte enable output valid time 12 ns t 9 write byte enable output hold time 3 ns t 10 read/write output valid time 12 ns t 11 read/write output hold time 3 ns t 12 data input setup time 7 ns t1 t3 t2 t4 valid t5 t6 t7 t8 t9 twt +1 t12 t13 t14 t15 valid internal sysclk bi_address bi_cs bi_oe bi_wbe bi_data (to stb03xxx) bi_data (from stb03xxx) t10 t11 bi_r/w output output output output input output output output
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 39 of 54 sdram interface timing diagram sdram interface timing values t 13 data input hold time 3 ns t 14 data output valid time 15 ns t 16 data output hold time 3 ns symbol parameter min max units t 1 sd_clk clock period (at sysclk = 54 mhz) 9.25 ns t 2 output valid time 7.25 ns t 3 output hold time 1ns t 4 input setup time 1ns t 5 input hold time 2.5 ns notes: t rcd = (2, 3, or 4) x t1 C controlled by sdramc bank register bits [21:22] t ras = (5 or 6) x t1 C controlled by sdramc system register bit 4 t rp = (2, 3, or 4) x t1 C controlled by sdramc bank register bits [25:26] t rc = (7, 8, 9, or 10) x t1 C controlled by sdramc bank register bits [30:31] sram interface timing values (continued) symbol parameter min max units t1 t2 t3 valid t5 t4 output output input sdn_clk sdn_data, controls sdn_data
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 40 of 54 stb03_sds_0323.fm.00 march 23, 2000 video input interface timing video input timing values video output interface timing video output timing values symbol parameter min max units t 1 pixel clock period 37 ns t 2 output valid time 16 ns t 3 output valid time 4 ns t 4 input setup time 11 symbol parameter min max units t 1 pixel clock period 37 ns t 2 output valid time 15 ns t 3 output hold time 4 ns t1 t2 t3 valid dv_pixel_clock dv_data (gpio1:7) dv_data dv_vsync input input t1 t2 t3 valid dvn_pixel_clock dvn_data output output dvn_hsync dvn_vsync
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 41 of 54 transport input interface timing transport input interface timing values transport auxiliary output interface timing transport auxiliary output interface timing values symbol parameter min max units t 1 ci_clock period 15 ns t 2 input setup time 4 ns t 3 input hold time 3 ns symbol parameter min max units t 1 hsp_clock period (at sysclk = 54 mhz) 19.25 ns t 2 output valid time 10 ns t 3 output hold time 2 ns t1 t2 t3 valid ci_clock ci_data ci_packet_start ci_data_enable input input t1 valid t3 hsp_data_enable t2 hsp_data hsp_clock output output hsp_packet_start
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 42 of 54 stb03_sds_0323.fm.00 march 23, 2000 dvb-ci (pcmcia) interface timing note 1. refer to the sram timing diagram for dvb-ci output timing values on page (sram page). note 2. bi_ready can also be con?gured as an asynchronous input. audio output timing dvb-ci (pcmcia) interface timing values symbol parameter min max units t 1 input set-up time 5 ns t 2 input hold time 3 ns t 3 input set-up time 15 ns t 4 input hold time 2 ns valid valid valid t1 t2 t4 t3 valid valid 4 cycles 3 cycles 4 cycles 1 + twt th (if ready is not used) (th must be > 4 cycles) sysclk bi_address bi_data (output) bi_cs1 output input output output output interna l input signal bi_address [14] (pcmcia_iowr) bi_address [15] (pcmcia_iowr) bi_rw (pcmcia_we) rmi_oe (pcmcia_oe) bi_data (input) bi_ready (pcmcia_wait) int_cs (from ebiu) ] > t1 t2 t3 valid da_bit_clock da_lr_channel_clock, da_serial_data (0:2) output output
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 43 of 54 audio output timing values ieee 1284 timings compatibility mode handshake compatibility mode handshake timing values symbol parameter min max units t 1 da_bit_clock period (1/[64 x 48 khz]) 326 ns t 2 output valid time 18 ns t 3 output hold time 0 ns symbol parameter min max units t 1 host 750 ns t 2 strobe 750 ns 500 m s ns/ m s t 3 hold 750 ns t 4 ready 0 ns t 5 busy 500 ns t 6 reply 0 ns t 7 acknowledge (ack) 500 ns 10 m s ns/ m s t 8 nbusy 0 ns pdata nstrobe nack busy nselectin valid data t 1 t 1 t 1 t 1 t 1 t 1 t 1 t 1
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 44 of 54 stb03_sds_0323.fm.00 march 23, 2000 ieee 1284 mode handshake timing values nibble mode handshake note: see the table, ieee 1284 mode handshake timing values, for symbol values. symbol parameter min max units t h host response time 0 1 sec t infinite response time 0 infinite t l peripheral response time 0 35 ms t r peripheral response time (ecp mode only) 0 t p minimum setup or pulse width 0.5 m s m s t d minimum data setup time (ecp modes only) 0 hostbusy (nautofd) ptrclk (nack) 1284 active (nselectin) nerror select perror busy data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 tl tp t 8 tl tl tl th th tp tp th 8
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 45 of 54 byte mode handshake note: see the table, ieee 1284 mode handshake timing values, on page 44 for symbol values. ecp forward mode handshake note: see the table, ieee 1284 mode handshake timing values, on page 44 for symbol values. tl tp t 8 th tl tp th tp tl tp th tl tp hostbusy (ppu_nautofd) ptrclk (ppu_nack) hostclk (ppu_nstrobe) pdata ndataavail (ppu_nerror) ptr to host data available ptr to host data not available hostclk (nstrobe) pdata hostack (nautofd) periphack (busy) byte 0 byte 1 tl td th tr td ncmd ncmd t 8 t 8
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 46 of 54 stb03_sds_0323.fm.00 march 23, 2000 ecp reverse mode handshake note: see the table, ieee 1284 mode handshake timing values, on page 44 for symbol values. periphack (busy) pdata hostack (nautofd) periphclk (nack) nreverserequest (ninit) nackreverse (perror) byte 0 byte1 ncmd ncmd tl td th t 8 t 8 t 8 t 8 t 8 td tl th t 8
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 47 of 54 negotiation phase note: see the table, ieee 1284 mode handshake timing values, on page 44 for symbol values. iic timing iic timing values note: sda and scl outputs are open-drain. symbol parameter min max units t 1 output valid time (falling edge) 15 ns 1284 active (ppu_nselectin) hostbusy (ppu_nautofd) pdata hostclk (ppu_nstrobe) ptrclk (ppu_nack) ndataavail (ppu_nerror) ackdatareq (ppu_perror) xflag (select) t 8 tp tl th t 8 tp tp tp tl extensibility data byte sys clk iic_sda t1 t1 iic_scl output output output
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 48 of 54 stb03_sds_0323.fm.00 march 23, 2000 smart card (sci) timing sci timing values t1 = (2 x scclk_cnt0) sysclk periods t2 = bit width = variable from 32 to 512 sc_clk periods = scetu x sc_clk periods note: sc_detect, sc_reset, sc_select, and sc_vcc_command are synchronous to the system clock and are not shown here. modem serial interface timing modem codec timing values symbol parameter min max units t 1 input setup time 15 ns t 2 input hold time 3 ns t 3 output hold time 3 ns t 4 output valid time 16 ns sysclk sc_clk scn_io t1 t2 output output t4 t1 t1 t1 t2 t2 t3 t4 output input input input input output t3 modem_clk modem_clk modem_rxd modem_fr modem_txd modem_fr
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 electrical information page 49 of 54 note 1. modem_clk can be con?gured to send and receive data on the rising or falling clock edge. note 2. modem_fr can be an input or an output. serial control port timing scp timing values note: this timing diagram assumes the ci bit in the scp spmode register is set to 0. if ci is set to 1, the lk signal is inverted. symbol parameter min max units t 1 smc_clk period 80.8 ns t 2 output valid time 12 ns t 3 output valid time 13 ns t 4 output hold time 4 ns t 5 input setup time 10 ns t 6 input hold time 3 ns internal sysclk smc_clk smc_txd smc_rxd t2 t3 t4 t5 t6 t1 output output input
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary electrical information page 50 of 54 stb03_sds_0323.fm.00 march 23, 2000 additional timing information interface timing information iic compliant with philips semiconductors i 2 c specification, dated 1995. interface is asynchronous. direct connect smart card (sc) compatible with iso/iec 7816-3. interface is asynchronous. direct connect. serial0/16550 functionally identical to national semiconductor ns16450 in character mode (after reset). interface is asynchronous. external transceiver logic is required. serial1/infrared functionally identical to ibm powerpc403 ? serial port unit (spu) (after reset). compatible with the irda specification 1.1 irda 1.0 sir with data rates up to 115.2 kbps irda 1.1 fir with data rates up to 1.152 mbps interface is asynchronous external transceiver logic is required external interrupts inputs are asynchronous dma external dma request inputs are asynchronous gpt capture timer inputs are asynchronous external bus master interface is asynchronous riscwatch compatible with ibm riscwatch probe direct connect to probe contact your ibm applications engineer for more information risctrace compatible with ibm risctrace probe direct connect to probe contact your ibm applications engineer for more information
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 mechanical information page 51 of 54 mechanical information package diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 15.5 a .050 1.27 1.1 27.94 1.22 31 .610 12.75 [0,502] ac ab aa y w v u t r p n m l k j h g f e d c b a e 1 1 0 0 5 l 2 8 7 5 0 1 12.75 [0,502] 15.5 b .050 1.27 1.1 27.94 1.22 31 .610 0. 20/. 008 m top of package (bga side down) oem p/n 0.15 c c 0.25 c e52p substrate cu stiffener (304x ? 0. 0.15 solder ball c ? 0.30 ? 0.10 c a b m glob top ibm p/n xxxxxxx date code ibm39 stb03xxx xxx xxx powerpc a digital set-top box integrated controller zzwwmmmm bottom of package (bga side up) cavity
ibm39stb032xx IBM39STB034XX stb032xx and stb034xx digital set-top box integrated controllers preliminary development support page 52 of 54 stb03_sds_0323.fm.00 march 23, 2000 development support with ibm tools and the ibm powerpc embedded tools program, you receive the support you need to develop and debug your stb applications quickly. ibm tools ibm offers windows 95/98 - hosted development tools for stb applications that include: ? stb and processor reference design and evaluation kits, including board, compiler, debugger, rom source, schematics, etc. ? riscwatch debugger, with in-circuit, rom monitor, rtos-aware debugging and real-time non-invasive trace capability ? metaware high c/c++ compiler, highly optimized for the powerpc processors debug the stb03xxx facilitates development through its jtag test access port. with ibm riscwatch or other third-party debugger on a workstation, you can single-step the processor and interrogate the internal processor state. additionally, the real-time debug port supports tracing the executed instruction stream out of the instruction cache. the trace status signals provide trace information in real-time instruction trace debug mode. this mode does not alter the performance of the processor. third-party tool support through the ibm powerpc embedded tools program, you have access to hundreds of tools offered by over 75 industry-leading vendors. often, the tools you currently use support powerpc embedded processor prod- ucts, such as the ibm stb010xx digital set-top box integrated controllers. for a list of the tools that are offered, visit ibms tool support web page at: http://www.chips.ibm.com/products/powerpc/tools/ note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design.
ibm39stb032xx IBM39STB034XX preliminary stb032xx and stb034xx digital set-top box integrated controllers stb03_sds_0323.fm.00 march 23, 2000 revision log page 53 of 54 revision log revision contents of modi?cation march 23, 2000 initial release (revision 00).
copyright and disclaimer copyright international business machines corporation 2000. all rights reserved printed in the united states of america february 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both: ibm ibm logo coreconnect powerpc logo powerpc 405 dolby is a trademark of dolby laboratories. java and all java-based trademarks and logos are trademarks or registered trademarks of sun microsystems, inc. in the united states and/or other countries. windows is a trademark of microsoft corporation in the united states and/or other countries. other company, product, and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm's product specifications or warran- ties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is pre- sented as an illustration. the results obtained in other operating environments may vary. product name is subject to change. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com stb03_sds_0323.fm.00 march 23, 2000 a

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